1. Field of the Invention
The invention relates to a manufacturing method of Schottky barrier diode device made of a compound semiconductor and applied in a high frequency circuit, specifically to a manufacturing method of Schottky barrier diode having a planar configuration to achieve a smaller operation region and overall chip size.
2. Description of the Related Art
The demand for high frequency devices has been rapidly increasing due to the expanding market for portable telephones and digital satellite communication equipment. Many of such devices include field effect transistors (referred to as FET, hereinafter) employing a gallium arsenide (referred to as GaAs, hereinafter) substrate because of its excellent high frequency characteristics. Typical application in this field includes local oscillation FETs for satellite antenna and monolithic microwave integrated circuits (MMIC) in which a plurality of FETs are integrated for wireless broadband. GaAs Schottky barrier diodes are also used in base stations of cellular phone system.
FIG. 1 is a cross-sectional view of an operation region of a conventional Schottky barrier diode. An n+ epitaxial layer 22 (a silicon impurity concentration of about 5xc3x971018 cmxe2x88x923) having a thickness of about 6 xcexcm is formed on an n+ GaAs substrate 21. An n epitaxial layer 23 (a silicon impurity concentration of about 1.3xc3x971017 cmxe2x88x923) having a thickness of about 350 nm is formed on the n+ epitaxial layer 22. This n epitaxial layer serves as an operation region.
An ohmic electrode 28 makes a ohmic contact with the n+ epitaxial layer 22 and is made of a AuGe (gold-germanium alloy)/Ni (nickel)/Au (gold) metal layer disposed as a first wiring layer. A Ti (titanium)/Pt (platinum)/Au metal layer 32 serves as a second wiring layer, and is divided into wiring on the anode side and wiring on the cathode side. On the anode side, the Ti/Pt/Au metal layer makes a Schottky contact with the n epitaxial layer 23, and forms a Schottky contact region 31a. The portion of the Ti/Pt/Au metal layer on the anode side above the Schottky contact region 31 a is referred to as a Schottky electrode 31 hereinafter. An anode electrode 34 is formed on and completely overlaps the Schottky electrode 31 and its extension. The anode electrode 34 provides an anode bonding pad and is formed by Au plating using the Schottky electrode 31 and its extension as a plating electrode. The Au metal layer serves as a third wiring layer. On the cathode side, the cathode electrode 35 provides a cathode bonding pad and is formed of the Au layer. The Ti/Pt/Au metal layer on the cathode side directly contacts the ohmic electrode 28. The edge of the Schottky electrode 31 needs to be on a top surface of a polyimide layer 30 to satisfy photolithographic requirements. Accordingly, a portion of the Schottky electrode 31, near the Schottky region 31a, overlaps by about 16 xcexcm with the polyimide layer 30 formed on the ohmic electrode 28 on the cathode side. The entire substrate and epitaxial layers are at a cathode voltage except the Schottky contact region 31a. The polyimide layer 30 insulates the anode electrode 34 from the substrate 21 and the epitaxial layers. The crossing area between the anode electrode 34 and the underlining structure is about 1300 xcexcm2, which could provide a large parasitic capacitance to the device if the thickness of the polyimide layer 30 is small. Thus, to have a reasonably small parasitic capacitance, the thickness of the polyimide layer must be as large as 6-7 xcexcm even though the polyimide film 30 has a relatively low dielectric constant.
The n epitaxial layer 23 of the lower impurity concentration (1.3xc3x971017 cmxe2x88x923) is necessary for assuring a Schottky contact region 31a with good Schottky characteristics and a high breakdown strength (10V). The ohmic electrode 28 is formed directly on the n+ epitaxial layer 22 for reducing the resistance at the contact. For this reason, a mesa etching process is necessary for exposing the top surface of the n+ epitaxial layer 22. The n+ GaAs substrate 21 underneath the n+ epitaxial layer 22 also has a high impurity concentration, and has a backside electrode made of the AuGe/Ni/Au metal layer for an external contact from the backside.
FIG. 2 is a schematic top view of the conventional Schottky barrier diode having the operation region shown in FIG. 1. The Schottky contact region 31 a formed on the n epitaxial layer 23 occupies a central portion of the device. The diameter of this region 31a is about 10 xcexcm. A Schottky contact hole 29 is formed in the center of the Schottky contact region 31a. The Ti/Pt/Au metal layer of the second wiring layer is in direct contact with the n epitaxial layer 23 through the contact hole 29. The ohmic electrode 28 of the first wiring layer surrounds the circular Schottky contact region 31a, and occupies almost a half of the top surface of the device.
The Au metal layer of the third wiring layer provides bonding pads. On the anode side, the pad area is the minimum area allowed for wire bonding. On the cathode side, the pad area is large enough to provide multiple wire bonding, which is required for reducing the inductance generated at the bonding pad. The area of the anode bonding pad is about 40xc3x9760 xcexcm2 and the area for the cathode bonding pad is about 240xc3x9770 xcexcm2.
However, the mesa etching, which is required to expose the n+ epitaxial layer 22 through the n epitaxial layer 23 above for the direct contact with the ohmic electrode 28, is not stable enough to provide accurate patterning of the device. For example, the wet etching process used in the mesa etching may remove the oxide film 25 around the contact hole 29, leading to formation of mesa with an irregular shape. Such an irregular mesa structure may cause adverse effects on the Schottky barrier diode, especially the characteristics of the Schottky contact region 31a. 
Furthermore, the polyimide layer 30 has a thickness as large as 6-7 xcexcm to reduce the parasitic capacitance generated between the Schottky electrode 31 and the underlining structures (the epitaxial layers 22, 23 and the substrate 21) at the cathode voltage. To form a step coverage of this thick polyimide layer 30 by the electrodes 31, 34, 35, the edges of the polyimide layer 30 near the Schottky contact region 31 a must have a tapered cross-section, as shown in FIG. 1. Such a tapered structure gives rise to a variation of the tapering angle, typically between 30 and 45 degrees. To accommodate this variation, a long separation between the Schottky contact region 31a and the ohmic electrode 28 is required. This separation leads to a large resistance and, thus, poor high frequency characteristics. The device shown in FIG. 1 has a separation of about 7 xcexcm.
The invention provides a manufacturing method of Schottky barrier diode including providing a substrate made of a compound semiconductor, and epitaxially growing a first layer of a conduction type on the substrate. The method also includes implanting impurities into a predetermined region of the first layer to form an impurity-implanted region of the conduction type, forming a first electrode making an ohmic contact with the impurity-implanted region, and forming a second electrode making a Schottky contact with the first layer. This step is followed by forming a first metal wiring connected to the first electrode for external connection, and forming a second metal wiring connected to the second electrode for external connection.
The invention also provides a manufacturing method of Schottky barrier diode including providing a substrate made of a compound semiconductor, and epitaxially growing a first layer of a conduction type on the substrate. The method also includes implanting impurities into a predetermined region of the first layer to form an impurity-implanted region of the conduction type, and forming an electrode making an ohmic contact with the impurity-implanted region. The step further includes forming a patterned metal layer making a Schottky contact with the first layer and being in contact with the electrode. The patterned metal layer includes a first metal wiring from the electrode and a second metal wiring from the Schottky contact.
The invention further provides a manufacturing method of Schottky barrier diode including providing a substrate made of a compound semiconductor, implanting first impurities into a first predetermined region of the substrate to form an operation region of a conduction type, and implanting second impurities into a second predetermined region of the substrate to form an impurity-implanted region of the conduction type adjacent to the operation region. The method also includes forming a first electrode making an ohmic contact with the impurity-implanted region, and forming a second electrode making a Schottky contact with the operation region. The method further includes forming a first metal wiring connected to the first electrode for external connection, and forming a second metal wiring connected to the second electrode for external connection.
The invention also provides a manufacturing method of Schottky barrier diode including providing a substrate made of a compound semiconductor, implanting first impurities into a first predetermined region of the substrate to form an operation region of a conduction type, and implanting second impurities into a second predetermined region of the substrate to form an impurity-implanted region of the conduction type adjacent to the operation region. The method also includes forming an electrode making an ohmic contact with the impurity-implanted region, and forming a patterned metal layer making a Schottky contact with the operation region and being in contact with the electrode. The patterned metal layer includes a first metal wiring from the electrode and a second metal wiring from the Schottky contact.